Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors
📜 Abstract
Memory isolation is a key property of a reliable and secure computing system — an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row’s wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors.
✨ Summary
Summary
This paper provides the first detailed, real-system demonstration and broad characterization of what became known as the RowHammer vulnerability. Repeatedly activating and precharging DRAM rows can cause charge leakage and bit flips in nearby victim rows, violating memory-isolation assumptions. Across 129 DDR3 modules, the authors observed disturbance errors in 110 modules and showed that a user-level program could induce errors on Intel and AMD systems. The paper also proposed PARA (probabilistic adjacent row activation), a stateless mitigation that refreshes neighboring rows with low probability and was estimated to impose very little performance overhead. (people.inf.ethz.ch)
The paper directly influenced subsequent security research. In 2015, Google Project Zero explicitly built on this work to demonstrate RowHammer-based privilege-escalation exploits, including corruption of page-table entries and a Native Client sandbox escape. (googleprojectzero.blogspot.com) Google also released an open-source userland RowHammer testing program based on the problem described by the paper. (github.com) Later retrospective research identifies this paper as the starting point for extensive follow-up work on RowHammer attacks, DRAM characterization, and mitigation mechanisms. Subsequent work examined techniques including double-sided hammering, remote and browser-based attacks, Target Row Refresh, and newer hammering methods such as Half-Double. (arxiv.org) Industry-facing documentation also records DRAM mitigations such as targeted row refresh and maximum-activate-count mechanisms in later memory standards. (googleprojectzero.blogspot.com)