Anis Koubâa, André Cunha, Mário Alves, Eduardo Tovar - "<a>TDBS: a time division beacon scheduling mechanism for ZigBee cluster-tree wireless sensor networks</a>"
Article will be presented by Ranulfo Plutarco Bezerra Neto
Synchronization is a challenging and important issue for time-sensitive Wireless Sensor Networks (WSN) since it requires a mutual spatiotemporal coordination between the nodes. In that concern, the IEEE[masked]/ZigBee protocols embody promising technologies for WSNs, but are still ambiguous on how to efficiently build synchronized multiple-cluster networks, specifically for the case of cluster-tree topologies. In fact, the current IEEE[masked]/ZigBee specifications restrict the synchronization to beacon-enabled (by the generation of periodic beacon frames) star networks, while they support multi-hop networking in mesh topologies, but with no synchronization. Even though both specifications m…
Jorge Biolchini, Paula Gomes Mian, Ana Candida Cruz Natali and Guilherme Horta Travasssos - "Systematic Review in Software Engineering"
The term Systematic Review (SR) is used to refer to a specific methodology of research, developed in order to gather and evaluate the available evidence pertaining to a focused topic.In contrast to the usual process of literature review, unsystematically conducted whenever one starts a particular investigation, a SR is developed, as the term denotes, in a formal and systematic way. This means that the research conduction process of a systematic type of review follows a very well defined and strict sequence of methodological steps, according to an aprioristically developed protocol. This instrument is constructed around a central issue, which represents the core of the investiga…
Luiz AndrC Barroso, Kourosh Gharachorloo, Robert McNamarat, Andreas Nowatzyk, Shaz Qadeert, Barton Sano, Scott Smith, Robert Stets, and Ben Verghese - "PIRANHA: A scalable architecture based on single-chip multiprocessing"
Article will be presented by Alan Jheyson Ribeiro da Costa
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instructionlevel parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that comercia1 applications constitute by far the most important market for high-…